A conventional integrated circuit contains a plurality of metal lines separated by inter-wiring spacings, which metal lines include bus lines, bit lines, word lines, logic interconnect lines, and the like. Typically, the metal lines of vertically spaced metallization layers are electrically interconnected by vias. Metal lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of this type, according to current technology, may include eight or more levels of metallization layers in order to satisfy device geometries and micro miniaturization requirements.
FIGS. 1 and 2 illustrate a connection to a conventional NAND flash memory array. Referring to FIG. 1, the array includes a plurality of active regions 102 laid out parallel to each other. Active regions 102 are separated by shallow trench isolation regions 104. A plurality of word-lines 106 is formed over and perpendicular to active regions 102. Word-lines 106 also act as the gate electrodes of metal-oxide-semiconductor (MOS) devices, and thus a plurality of flash memory cells 107, which are connected in series, are formed. Select source gate 108 and select drain gate 110 are formed on opposite sides of flash memory cells 107.
FIG. 2 illustrates the formation of bit-lines 112 in the bottom metallization layer. Each of the bit-lines 112 is connected to one of active regions 102 through contacts 114. Accordingly, bit-lines 112 are vertically aligned to active regions 102, and typically have a same width W1 and a same spacing S1 as the underlying active regions 102. Assuming active regions 102 have width W1 and spacing S1. Preferably, to reduce the area occupied by the memory, width W1 and spacing S1 are both equal to the minimum feature size of the respective formation technology. For 30 nm and 40 nm technologies, the minimum feature sizes are 30 nm and 40 nm, respectively.
When the minimum feature size of integrated circuits is reduced to about 30 nm to about 40 nm, the dimensions of metal lines in metallization layers are also scaled down accordingly. However, this causes several problems. First, the mean free path of electrons is about 39 nm. When the dimensions of the copper interconnects, such as bit-lines 112, approach the mean free path of electrons, the resistivity of the interconnect structure significantly increases. Accordingly, the RC delay in the interconnect structure significantly increases. Second, when copper is filled into via openings and trench openings, copper void will become a major problem. In 30 nm and 40 nm technologies, these problems have become gating issues.
FIGS. 1 and 2 demonstrated the problem of increasing resistivity of copper lines cannot be solved by increasing the width of metal lines in conventional interconnect formation schemes. This is because the width and spacing of metal lines are limited by the dimensions of the underlying integrated circuits. Accordingly, new structures and methods for solving the above-discussed problems are needed.